1. Field of the Invention
This invention generally relates to methods and configurations of microelectronic topography fabrications and, more particularly, to methods and configurations of microelectronic topography fabrications having a barrier layer formed therein.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
In some microelectronic devices, a metallization structure may include, in addition to a bulk metal feature, one or more barrier layers arranged above, below, and/or along the sides of the bulk metal feature to prevent elements within the bulk metal feature from diffusing to underlying and/or overlying layers of the topography. Although conventional barrier layers are generally sufficient to inhibit most elemental diffusion from a bulk metal feature, some diffusion may still occur. For example, copper atoms are particularly notorious for being able to migrate through barrier layers. The migrated copper atoms can potentially be exposed to oxidation or moisture at the surface of the barrier layer or may tunnel through silicon materials disposed adjacent to the barrier layer, affecting the reliability of the device and, in some cases, causing the device to malfunction. A further deficiency of conventional barrier layers is that an agglomeration of vacancies at weak interfaces between the bulk metal feature and the barrier layers may be induced by stresses within the barrier layers. In particular, barrier layers formed having compressive stress may undesirably cause hillocks to form within the barrier layer structure, causing nonplanarity within the upper surface of the barrier layer. Alternatively, barrier layers formed having tensile stress may potentially result in delamination of the barrier layer from the bulk metal feature.
The addition of barrier layers may also complicate the fabrication of a device, incurring increased process steps, processing time, and costs. For instance, additional steps, such as cleaning contamination from the topography, may be needed prior to or subsequent to the fabrication of a barrier layer to inhibit undesirable effects to the functionality of the device. In particular, a barrier layer may become oxidized in between processes subsequent to deposition in some embodiments. Removal of such oxidation to prevent an increase in resistivity of the metallization structure, however, may cause the surface of the barrier layer to be etched, removing particles of the barrier layer. In some cases, the particles of the barrier layer may cause further debris by depositing on to the interlevel dielectric surface adjacent to the metallization structure. In addition or alternatively, small fragments of the bulk metal layer may be formed upon an adjacent dielectric layer, such as in embodiments in which the bulk metal feature is polished to be confined within sidewalls of the dielectric layer. In any case, the residual particles may be sealed with the deposition of an overlying interlevel dielectric, possibly incurring leakage current at a higher voltage potential.
The problem of the small metal fragments on the dielectric layer adjacent to the bulk metal feature may be further compounded when electroless deposition techniques are used to selectively deposit a barrier layer on the bulk metal feature. Electroless deposition (also referred to herein as “electroless plating”) is a process for depositing materials on a catalytic surface from an electrolyte solution without an external source of current. An advantage of an electroless plating process is that it can be selective, i.e., the material can be deposited only onto areas that demonstrate appropriate chemical properties. In particular, local deposition can be performed onto metals that exhibit an affinity to the material being deposited or onto areas pretreated or pre-activated, e.g., with a catalyst. Any residual fragments on surfaces of an adjacent dielectric layer may be catalytic to the electroless deposition of the barrier layer or may attract a catalytic seed layer used to electrolessly deposit the barrier layer. In either case, portions of the barrier layer may be undesirably deposited upon the adjacent dielectric structure, potentially causing a short within the circuit.
Some methods for removing metal residue upon a dielectric surface may include etching the dielectric with hydrofluoric acid and/or a brush scrub. Such methods, however, have a tendency to damage the metal layers on the topography. In addition, hydrofluoric acid cleaning is generally only constructive for cleaning silicon-oxide based interlevel dielectrics which do not have a low dielectric constant (k). In particular, low-k dielectric materials (referred to herein as dielectric materials having a dielectric constant less than approximately 3.5) are generally porous and, therefore, may undesirably retain hydrofluoric acid during a cleaning process, which may in turn cause the dielectric layer to deteriorate in time. In addition, carbon-based low-k dielectric materials are generally resistant to cleaning by hydrofluoric acid. Consequently, as the use of low-k dielectric materials become more prevalent within microelectronic topographies, such cleaning techniques may be insufficient.
It would, therefore, be desirable to develop methods for removing metallic particles from dielectric surfaces while avoiding the aforementioned problems. In addition, it would be beneficial to inhibit the formation of metallic debris during the fabrication of a metallization structure. Furthermore, it would be advantageous to develop barrier layer configurations which inhibit a greater degree of elemental diffusion from overlying and/or underlying metal features than provided by conventional barrier layers. Moreover, it would be desirable to develop a barrier layer configuration which is less susceptible to hillock formation or delamination.